Memory devices (which are sometimes referred to herein as “memories”) are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of a charge storage structure, such as floating gates or trapping layers or other physical phenomena, determine the data state of each cell. Common electronic systems that utilize flash memory devices include, but are not limited to, personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules, and the uses for flash memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a string of memory cells is coupled in parallel with each memory cell coupled to a data line, such as those typically referred to as digit (e.g., bit) lines. In NAND flash architecture, a string of memory cells is coupled in series with only the first memory cell of the string coupled to a bit line.
As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. However, in order to continue to reduce the costs of the system, the parts count must be kept to a minimum. This can be accomplished by increasing the memory density of an integrated circuit by using such technologies as multilevel cells (MLC). For example, MLC NAND flash memory is a very cost effective non-volatile memory.
As cells in a memory are cycled more and more times, their performance can be affected. For example, some cells will program or read differently if they have been cycled a large number of times. Also, data retention time can be affected for cells that have been cycled a large number of times. To reduce cycling issues, many memories use a process called wear leveling on blocks of a memory. Wear leveling ensures that all blocks get programmed and erased a similar number of times, over time. Program and erase cycles are distributed over all blocks of the memory, so that each block is stressed about the same, as opposed to one block being overly stressed while another is minimally stressed. Wear leveling virtually extends cycling endurance in memories. In a block swap, when a block reaches a certain wear amount, for example a pre-determined program/erase cycle count based, a subsequent erase request triggers a swap of the block logical addresses with a low cycle count block. If the block to be swapped for the high cycle count block is not empty, such a swap requires two erase phases.
Swap functionality is implemented, for example, using a programmable hardware device called a block mapping unit (BMU) that is in the address path of the memory. The BMU manages logical addresses for the memory, and logical address remaps. Each physical block of the memory has a memory area dedicated to a program/erase cycle count. At each erase event, a physical block that is being cycled is checked for wear leveling necessity. When wear leveling is indicated, a swap of the block to be wear leveled is made with a low-cycled block, and logical re-mapping is performed by the BMU. Wear leveling is hidden, so some programmable part of the memory and software is typically dedicated to power loss management, allowing an aborted wear leveling operation to be recovered at the next power-up.
In typical memories, hierarchy stops at the block level. It is not possible to erase a section smaller than a block. Some new memories (e.g., page flash memories) are erasable on a level smaller than a block. For example, a sub-sector of a block is erasable in some memories. However, in such memories, the sub-sectors in a block consist of a subset of the block's word lines and share the same physical columns, but have separate program/erase access. As such, each sub-sector also has separate cycling and wear statistics. In page flash memories, each access in a program/erase operation to a sub-sector produces some effect on the other sub-sectors sharing the same block, in terms of data integrity. This data degradation affects wear leveling on the sub-sector level.
For the reasons stated above and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for improved wear leveling in memories.